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ISL97675
digital counter. As a result, any decimal value of (255/N) will be
discarded. For example for N = 4, ( 255/N ) = 63, thus:
Table 1 shows the PWM Dimming with Phase Shift and Direct
PWM Dimming configurations.
t D1 = t FPWM × ----------
t D2 = t FPWM × ----------
63
255
66
255
(EQ. 8)
RFWM/
DIRECTPWM
TABLE 1.
FUNCTION
PHASE
SHIFT
Dimming
Resolution
where t FPWM is the sum of t ON and t OFF . N is the number of active
channels. The ISL97675 will detect the numbers of active
channels automatically and is illustrated in Figure 24 for 4-
channel.
Connects with
Resistor
Floating
PWM Dimming with
frequency adjust
DirectPWM without
frequency adjust
Yes
No
8-bit
N/A
t PWMIN
Switching Frequency
PWMI
ILED1
ILED2
ILED3
60%
t D1
t D1
t FPWM (t PWMOUT )
t OFF
t ON
60% 40%
t D1
When the FSW/PhaseShift pin is biased from VDDIO with a
resistor divider R UPPER and R LOWER , the switching frequency and
phase shift function will change according to the following
FSW/PhaseShift levels shown in Table 2 with the recommended
R UPPER and R LOWER values .
TABLE 2.
ILED4
t D1
FSW/PHASE
SHIFT LEVEL
0 ~ 0.25 * VDDIO
SWITCHING
FREQUENCY
1.2MHz
PHASE
SHIFT
Yes
R UPPER
(k ? )
Open
R LOWER
(k ? )
0
ILED1
t D2
t D1 = Fixed Delay with Integer only while the decimal value
will be discarded (e.g. 63.75 = 63)
0.25 * VDDIO ~ 0.5 * VDDIO
0.5 * VDDIO ~ 0.75 * VDDIO
0.75 * VDDIO ~ VDDIO
1.2MHz
600kHz
600kHz
No
No
Yes
150
100
0
100
150
Open
FIGURE 24. 4 EQUAL PHASE CHANNELS PHASE SHIFT
ILLUSTRATION
Inrush Control and Soft-Start
The ISL97675 has separate built-in independent inrush control and
6.66 × 10
PWM Dimming Frequency Adjustment
The dimming frequency is set by an external resistor at the
RFPWM/DirectPWM pin to GND:
7
RFPWM
F PWM = ------------------------
(EQ. 9)
soft-start functions. The inrush control function is built around the
short circuit protection FET, and is only available in applications which
include this device.
After an initial delay from the point where the master Fault
Protection FET is turned on, it is assumed that inrush has
completed. At this point, the boost regulator will begin to switch
where FPWM is the desirable PWM dimming frequency and
R FPWM is the setting resistor. Do not bias RFPWM/DirectPWM if
direct PWM dimming is used, see Table 1 for clarification.
The PWM dimming frequency can be set or applied up to 30kHz
with duty cycle from 0.4% to 100%. The lower limit of 0.4% is the
result of 8-bit digitizer resolution.
Direct PWM Dimming
The ISL97675 can also operate in direct PWM dimming mode
such that the output follows the input PWM signal without phase
shifting. To use Direct PWM mode, users should float
RFPWM/DirectPWM pin. The input PWM frequency should be
limited to 30kHz and the minimum duty cycle be calculated by
the following Equation 10:
and the current in the inductor will ramp-up. The current in the
boost power switch is monitored and the switching is terminated
in any cycle where the current exceeds the current limit. The
ISL97675 includes a soft-start feature where this current limit
starts at a low value (275mA). This is stepped up to the final 2.2A
current limit in 7 further steps of 275mA. These steps will
happen over at least 8ms, and will be extended at low LED PWM
frequencies if the LED duty cycle is low. This allows the output
capacitor to be charged to the required value at a low current
limit and prevents high input current for systems that have only a
low to medium output current requirement.
For systems with no master fault protection FET, the inrush
current will flow towards C OUT when V IN is applied and it is
determined by the ramp rate of V IN and the values of C OUT and
boost inductor, L.
Min Duty Cycle = 350ns × Input PWM Frequency
(EQ. 10)
Fault Protection and Monitoring
For example, for a 200 Hz input PWM frequency, the minimum
duty cycle is:
The ISL97675 features extensive protection functions to cover all
the perceivable failure conditions. The failure mode of an LED
can be either open circuit or as a short. The behavior of an open
Min DC = 350ns × 200Hz = 0.007%
14
(EQ. 11)
circuited LED can additionally take the form of either infinite
FN7630.1
September 14, 2011
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